The heart of the MAC unit is the multiplier. Multipliers are the fundamental components in all digital processing systems. Many research efforts have been devoted to reducing the power dissipation of different multipliers. The largest contribution to the power consumption in a multiplier is due to generation and reduction of partial products. Among multipliers, tree multipliers are used in high speed applications such as filters, but these require large area. The carry-select-adder (CSA)-based radix multipliers, which have lower area overhead, employ a greater number of active transistors for the multiplication operation and hence consume more power. Hence in this work, proposing a new power aware VLSI architecture for 16 bit multiplication process for DADDA multiplier in a schematic editor using tanner tool, T-spice is used as simulator and w-editor is used for formal verification of the multiplier.