International Journal of Computer Science & Engineering Technology

ISSN : 2229-3345

Open Access
Open Access

ABSTRACT

Title : A NEW VLSI ARCHITECTURE OF PARALLEL MULTIPLIER BASED ON RADIX-4 MODIFIED BOOTH ALGORITHM USING VHDL
Authors : RASHMI RANJAN, PRAMODINI MOHANTY
Keywords : Multiplier and accumulator, booth algorithm, Digital Signal Processing (DSP) and standard design.
Issue Date : April 2012
Abstract :
Low power consumption and smaller area are some of the most important criteria for the fabrication of DSP systems and high performance systems. Optimizing the speed and area of the multiplier is a major design issue. However, area and speed are usually conflicting constraints so that improving speed results mostly in larger areas. In our project we try to determine the best solution to this problem by comparing a few multipliers. This project presents an efficient implementation of high speed multiplier using the shift and adds method, Radix-4 modified Booth multiplier algorithm. The parallel multipliers like radix 2 and radix 4 modified booth multiplier does the computations using lesser adders and lesser iterative steps. As a result of which they occupy lesser space as compared to the serial multiplier. This is very important criteria because in the fabrication of chips and high performance system requires components which are as small as possible
Page(s) : 147-154
ISSN : 2229-3345
Source : Vol. 3, Issue.04

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