Field Programmable Gate Arrays (FPGAs) are special type processor which allows the end user to configure directly. This paper investigates to design a low power reconfigurable Asynchronous FPGA cells. The proposed design combines four-phase dual-rail encoding and LEDR (Level-Encoded Dual-Rail) encoding with sleep controller. Four-phase dual-rail encoding is used for small area and low power of logic blocks, where LEDR encoding is used for high throughput and low power of data transfer and the sleep controller is used to reduce the standby power that is being consumed by the CLB. The circuit is simulated using the Xilinx Tool.