Power dissipation became a major challenge in Integrated Circuit (IC) design for both high-performance and portable applications. In the high-performance and high-density chips such as microprocessors, high power dissipation limits the number of on-chip transistors and increases the required heat removal, which tends to lower the performance and increase the system cost, size and weight. Logical effort technique gives the gate sizing scheme that minimizes the delay at the lowest cost of power or it minimizes the power dissipation for a given delay budget. Designing a circuit to achieve the greatest speed or to meet a delay constraint presents a bewildering array of choices. Which of several circuits that produce the same logic function will be fastest? How large should a logic gate’s transistors be to achieve least delay? Sometimes, adding stages to a path reduces its delay In proposed work, I have implemented logical effort technique in static CMOS circuits like conventional adder, array multiplier, decoder and multiplexer. These circuits are used very frequently in many bigger circuits. So if I change or adjust its transistors sizing such that its delay and PDP reduce then as a result of this bigger circuits also get the benefit of this changes.