The binary adders are the fundamental and key component in digital signal processors, general purpose microprocessors and data-processing application specific integrated circuits. Therefore, binary adders are crucial building blocks in very large scale integrated circuits. Their efficient implementation is highly important because a costly carry-propagation operation involving all operand bits has to be performed. With the increasing level of device integration and growth in complexity of microelectronic circuits, power dissipation, area and delay have become the predominant design goals for fast adder cells. In this paper, various 8-bit CMOS adder circuits are designed and implemented using TANNER EDA tool. The adder designs are simulated at different supply voltages and the results are compared to find an efficient adder structure. To minimize power-delay product a prefix adder has been proposed and compared with other adder structures. The results show that the proposed prefix adder has least power-delay product as compared to other adder designs. The proposed prefix adder has better results than the hybrid prefix adder in 180nm technology at 1.8V but in 90nm technology it has higher value of PDP at all voltages other than 2.5V.