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ABSTRACT
Title |
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Design and Simulation of Extended Golay
Code on FPGA for Long Distance Applications – A Review |
Authors |
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Mukta Thankachan, Bhagwat Kakde, Manish Jain |
Keywords |
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FPGA, syndrome, error pattern, Golay code, Extended Golay code, Encoding, Decoding, Hardware optimization |
Issue Date |
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Nov 2016 |
Abstract |
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FPGA is a portable and very powerful device to efficiently implementation the logic. This paper presents a general idea to provide security when data is on channels there is a possibility that it can be affected by some malicious function. To avoid this condition some encoding schemes were used like Hamming code, block code, Turbo codes, CRC-cyclic redundancy check-based etc. This paper presents a review on number of scholars work and coding scheme introduced in those papers is binary Golay code (G23) and extended binary Golay (G24).These codes were used for the fulfillment of required high speed with low-latency, higher security and less complexity architecture. The main purpose of this paper is to introduce a new scheme in future that can be implemented on FPGA using both binary Golay code (G23) and extended binary Golay (G24). |
Page(s) |
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445-448 |
ISSN |
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2229-3345 |
Source |
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Vol. 7, Issue.11 |
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